This paper presents an implementation

Abstraction: This paper presents an execution of Multistructure PIDFLC. Modification has been made to construction of the proposed PIDFLC in order to do it acts as PDFLC, PIFLC or PIDFLC depending on two external signals. Two versions of this accountant have been designed utilizing VHDL linguistic communication for FPGA execution. A new bundle has been designed in VHDL codification to implement trigonometric maps and fourth-order Runge-Kutta method to prove the proposed design with nonlinear systems. The accountant was able to bring forth an end product in 0.3 millisecond for additive workss and 0.7 millisecond for nonlinear works. Therefore, the proposed accountant will be able to command many systems with high trying rate.

Keywords: PIDFLC, FPGA execution, nonlinear systems, Altera.

Categorization: XYZ ( Electronic instrumentality and control )

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1. T. Jain, V. Patel and M.J. Nigam '' Execution of PID Controlled SIMO Process on FPGA Using Bacterial Foraging for Optimal Performance '' International Journal of Computer and Electrical Engineering, Vol. 1, No. 2, P: 1793-8198, June 2009.
2. V. Tipsuwanporn, S. Intajag and V. Krongratana '' Fuzzy Logic PID accountant based on FPGA for procedure control '' Proc. IEEE International Symposium on Industrial Electronics, Bangkok, Thailand, Vol. 2, pp. 1495-1500, 4-7 May 2004.
3. Obaid Z. A. , Sulaiman N. and M. N. Hamidon `` FPGA-based Execution of Digital Logic Design utilizing Altera DE2 Board '' International Journal of Computer Science and Network Security, VOL.9 No.8, P: 186-194, July 2009.
4. Obaid Z. A. , Sulaiman N. , M. H. Marhaban and M. N. Hamidon `` FPGA-Based Fuzzy Logic: Design and Applications - a Review '' International Journal of Engineering and Technology, vol. 1, figure 5, P: 491-502, December 2009.
5. Leonid Reznik, `` Fuzzed accountants '' , Newnes, first edition, 1997.

1. Introduction

The simplest and most usual manner to implement a fuzzed accountant is to recognize it as a computing machine plan on a general intent computing machine. However, a big figure of fuzzed control applications require a real-time operation to interface high-velocity restraints. Software execution of fuzzed logic on general purpose computing machines can non be considered as a suited design solution for this type of application higher denseness programmable logic devices such as FPGA can be used to incorporate big sums of logic in a individual IC. Semi-custom and full-custom application particular integrated circuit ( ASIC ) devices are besides used for this intent but FPGA provide extra flexibleness: they can be used with tighter time-to-market agendas [ 1 ] , [ 2 ] , [ 3 ] , [ 4 ] .

2. Layout of the Proposed Accountant

By and large, this accountant accept two types of end products, the first 1 is the works ( Yp ) and the 2nd 1 is the coveted end product ( Yd ) , both of them is digital signals, and present the control action signal as a digital end product. It besides accepts four 8-bit digital signals that represent the addition parametric quantities needed by the accountant ( relative addition Kp, derivative addition Kd, built-in addition Ki, and end product gain Ko ) , and other two one-bit signals to choose the type of the accountant ( PD fuzzy logic accountant, PI fuzzy logic accountant, or PID fuzzy logic accountant ) . Fig. 1 shows the general layout of the accountant bit in a unity feedback control system. Fuzzy accountant applications do non necessitate high truth. Accuracy of 6-9 spots is adequate and is rather sufficient for different applications. Many designed FIS french friess use this scope of spots [ 5 ] , since two versions of the accountant have been designed to do a comparing in which version is closest to Matlab-based design: the first one uses 6 spots for each input and end product variables, and 4 spots for rank grade, while the other uses 8 spots and 6 spots severally.

3. Structure of the Proposed PIDFLC

By and large, to stand for PID fuzzed logic accountant, it was required to plan a fuzzed illation system with three inputs that represent the proportional, derivative, and built-in constituents, and each one of them can hold up to eight fuzzy sets. So that the maximal figure of the needed fuzzy regulations to 83=512 regulations. To avoid this immense figure of regulations, the proposed accountant has been designed utilizing two parallel PD fuzzy logic accountants to implement the PID fuzzy logic accountant. The 2nd PDFLC has been converted to PIFLC by roll uping its end product. Fig. 1 shows the construction of proposed PID fuzzy logic accountant. Both accountants, PD fuzzy logic accountant and PI fuzzy logic accountant, receive the same mistake signal. The mistake signal is calculated by deducting works end product ( yp ) from the desired end product ( yd ) . The chief block in the PD fuzzy logic accountant is the fuzzed illation block. The proposed fuzzy illation block is two inputs, one end product fuzzy system of Mamdani type that uses singleton rank maps for the end product variable. The first input is the error signal vitamin E ( n ) , and the 2nd input is the rate of alteration of mistake signal defined as the difference between two back-to-back mistake values.

Before come ining the fuzzed illation block, each one of these two inputs have been multiplied by a addition coefficient inside the PD fuzzy accountant ( Kp and Kd or Kp and Ki ) . In similar mode, the end product of the fuzzed illation block is multiplied by a addition coefficient inside the PD fuzzy logic accountant, ( Ko ) . At the same clip, the end product of the fuzzed illation block in the 2nd PD fuzzy accountant is multiplied by a addition coefficient so accumulated to organize the uPIFLC. Both end products ( uPD and uPI ) are added together to organize the PIDFLC end product ( uPID ) . Since each PDFLC has its ain additions and regulations, the concluding design could work as a PDFLC, PIFLC or a PIDFLC ) depending on the two choice lines sw1 and sw0 -- -- , where, sw1sw0= 00, gives PD fuzzy logic accountant, sw1 sw0= 01 gives PI fuzzy logic accountant, and sw1 sw0=0x gives PID fuzzy logic accountant. The chief constituents in the proposed PD fuzzed logic accountant are: Input/Output block, Fuzzifier block, illation engine block, and Defuzzifier block.

4. Test Bench and Simulation Results

For the intent of simulation symmetric triangular fuzzy sets and singleton fuzzy sets with 8 lingual variables have been used for input and end product variable severally, in add-on to govern tabular array of 64 fuzzy regulations. At first, a trial is performed to do certain that the fuzzed illation system used inside the FPGA-based design is working decently This trial is performed to do certain that the fuzzed illation system used inside the FPGA-based accountant ( 6FBC or 8FBC ) is working decently. This trial involves bring forthing control surface utilizing fuzzed sets and regulation tabular array, this trial has been used to do a comparing between both types of FBC with Matlab-based ( MSBC ) , and shows that 8FBC is superior to 6FBC and it 's much close to MSBC.

Case Study 1: Second order theoretical account may stand for procedure such as place control of an ac motor [ 7 ] Equation ( 1 ) shows the mathematical works theoretical account, distinct transportation maps of this theoretical account has been obtained utilizing ZOH method, and the selected sampling period ( T ) is 0.52. The values of Kp, Kd, Ki, and Ko used in this trial were selected utilizing test and mistake.

The accountant gives action at 0.3 µs ; when PIDFLC applied for this system, as shown in Fig. 2, 8FBC response is near to the responses utilizing MSBC, with zero mistake and small overshot. The Average differences between MSBC and 6FBC for Step response and control action are -0.0256 and -0.0009 severally, and The Mean differences between MSBC and 8FBC for Step response and control action are -0.0030 and 0.0021 severally, since the 8FBC is superior to 6FBC and its much stopping point to MSBC.

Case Study 2: This instance is considered as a particular instance with the proposed design, because of VHDL accepts four mathematical operation merely, add-on, minus, division and generation, since it 's hard to stand for non-linear elements like trigonometric maps. In this instance, a mathematical theoretical account of nonlinear works has been used to prove the proposed accountant with unity feedback control system ; this theoretical account is characterized by Equation ( 2 ) and Equation ( 3 ) .

The first order filter on U to bring forth u represents an actuator. Assume the initial conditions y ( 0 ) = 0.1 radians ( = 5.73 deg. ) , y? ( 0 ) = 0, and the initial status for the actuator province is zero. For simulation of the fourth-order, Runge-Kutta method has been used with an integrating measure size of 0.01. Again, this works has been designed utilizing MATLAB package ( for simulation in MATLAB ) , and in non-synthesizable VHDL codification ( for simulation in ModelSim ) . A particular bundle was designed in VHDL codification to implement trigonometric maps and fourth-order Runge-Kutta method which are non available in Quartus II ( or in ISE ) criterion libraries. The values of Kp, Kd, Ki, and Ko used in this trial were selected utilizing test and mistake. The accountant gives action at 0.7 µs after the input latching. When utilizing nonlinear system for trial, both versions ( 6FBC and 8FBC ) supply by and large good responses though there is some oscillation. ( one must non be deceived by the steady province mistake that appears in Figure ( 4 ) , since it represents less than 1 % of the end product scope in the instance of 6FBC and less than 0.5 % of the end product scope, in the instance of 8FBC ) . The absolute mean difference between the nonlinear works response, utilizing MSBC, and the nonlinear works response, utilizing 6FBC, is less than 0.0155. The absolute mean difference between the nonlinear works response, utilizing MSBC, and the nonlinear works response, utilizing 8FBC, is less than 0.0085 as shown in Fig. 3.

5. Execution of the Proposed PIDFLC

The proposed PIDFLC has been implemented utilizing Altera DE2 board, this board offers a rich set of characteristics that make it suited for usage in a research lab environment for university and college classs and can used for any design executions, every bit good as for the development of sophisticated digital systems by utilizing hardware description linguistic communication ( HDL ) . All connexions are made through the Cyclone II 2C35 FPGA device in order to supply maximal flexibleness for the user. Therefore, the user can configure the FPGA to implement any system design.

6. Decision

Simulation environments have been built utilizing non-synthesizable VHDL codification for the intent of simulation in ModelSim, and the same design is coded in Matlab for the intent of simulation in Matlab ( MSBC ) . Two version of the accountant has been designed, the first one is 6-bits which uses 6-bits for each input/output variables ( 6FBC ) , while the 2nd uses 8-bits each input/output variables ( 8FBC ) . Two instance surveies have been used in order to prove this accountant. From these consequences, 8FBC is superior to 6FBC and it 's much close to MSBC. The accountant was able to bring forth an end product in 0.3 millisecond ( after input latching ) for additive workss and 0.7 millisecond for nonlinear works. Therefore, the proposed accountant will be able to command systems with high trying rate.

Recognitions

The writers would wish to thank foremost, our God, and all UPM staff and all friends who gave us any aid related to this work. Finally, the most thank is to our households and to our states which born us.

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