Seminar Report P Soc 5
CY8C52xxx) families are fully scalable 8-bit and 32-bit PSoC platform devices that share these characteristics: ¦ Fully pin, peripheral compatible ¦ Same integrated development environment software ¦ High performance, configurable digital system that supports a wide range of communication interfaces, such as USB, I2C, and CAN ¦ High precision, high performance analog system with up to 20-bit ADC, DACs, comparators, opamps, and programmable blocks to create PGAs, TIAs, mixers, etc. ¦ Easily configurable logic array ¦ Flexible routing to all pins ¦ High performance, 8-bit single-cycle 8051 (PSoC 3) or 32-bit ARM Cortex-M3 (PSoC 5) core .
1 Objective
8051 or Cortex-M3 Central Processing Unit (CPU) with a nested vectored interrupt controller and a high performance DMA controller. Several types of memory elements including SRAM, flash, and EEPROM. System integration features, such as clocking, a featurerich power system, and versatile programmable inputs and outputs
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2. Top Level Architecture
The PSoC 5 CPU subsystem is built around a 32-bit three stage pipelined ARM Cortex-M3 processor running up to 80 MHz. The PSoC 5 instruction set is the same as the Thumb-2 instruction set available on standard Cortex- M3 devices.
Three stage pipelining operating at 1. 25 DMIPS/MHz. This helps to increase execution speed or reduce power. Supports Thumb-2 instruction set: The Thumb-2 instruction set supports complex operations with both 16- and 32-bit instructions Atomic bit level read and write instructions Support for unaligned memory access Improved code density, ensuring efficient use of memory. Easy to use, ease of programmability and debugging: Ensures easier migration from 8- and 16-bit processors Nested Vectored Interrupt Controller (NVIC) unit to support interrupts and exceptions: Helps to achieve rapid interrupt response Extensive debug support including: Serial Wire Debug Port (SWD-DP), Serial Wire JTAG Debug Port (SWJ-DP) ? Break points ? Flash patch ? Instruction tracing ? Code tracing CONTROLLER The CPU subsystem includes a programmable Nested Vectored Interrupt Controller (NVIC), DMA (Direct Memory Access) controller, Flash cache ECC, and RAM. The NVIC of both PSoC 3 and PSoC 5 devices provides low latency by allowing the CPU to vector directly to the first address of the interrupt service routine, bypassing the jump instruction required by other architectures. The PSoC 5 interrupt controller also offers a few advanced nterrupt management capabilities, such as interrupt tail chaining to improve stack management with multiple pending interrupts providing lower latency. Supports 32 interrupt lines Programmable interrupt vector Configurable priority levels from 0 to 7 Support for dynamic change of priority levels Support for individual enable/ disable of each interrupt Nesting of interrupts Multiple sources for each interrupt line (can be either fixed function, UDB, or from DMA) Supports both level trigger and pulse trigger Tail chaining, late arrivals and exceptions are supported in PSoC® 5 devices
2. 1. Dma Controller
The DMA controller allows peripherals to exchange data without CPU involvement. This allows the CPU to run slower, save power, or use its cycles to improve the performance of firmware algorithms. Uses the PHUB for data transfer Includes 24 DMA channels Includes 128 transaction descriptors (TD) * Eight levels of priority per channel Transactions can be stalled or canceled Each transaction can be from 1 to 64 KB * Large transactions can be broken into smaller bursts of 1 to 127 bytes.Each channel can be configured to generate an interrupt at the end of transfer
In PSoC 5 devices, the flash cache also reduces system power consumption by reducing the frequency with which flash is accessed. The processor speed itself is configurable allowing for active power consumption tuned for specific applications. Instruction cache Direct mapped * 128 bytes total cache memory Registers for measuring cache hit/miss ratios Error correction code (ECC) support Error logging and interrupt generation. Designed to put flash into sleep automatically to save power
2. 2 Memory
The PSoC nonvolatile subsystem consists of Flash, bytewritable EEPROM, and nonvolatile configuration options.
The CPU can reprogram individual blocks of Flash, enabling boot loaders. An Error Correcting Code (ECC) can enable high reliability applications. A powerful and flexible protection model allows the user to selectively lock blocks of memory for read and write protection, securing sensitive information. The byte-writable EEPROM is available on-chip for the storage of application data. Additionally, selected configuration options, such as boot speed and pin drive mode, are stored in nonvolatile memory, allowing settings to become active immediately after power on reset (POR).
A Nonvolatile Latch (NVL or NV latch) is an array of programmable, nonvolatile memory elements whose outputs are stable at low voltage. It is used to configure the device at Power on Reset. Each bit in the array consists of a volatile latch paired with a nonvolatile cell. On POR release nonvolatile cell outputs are loaded to volatile latches and the volatile latch drives the output of the NVL. FEATURES A 4x8-bit NV latch for device configuration A 4x8-bit Write Once NV latch for device security PSoC® 3 and PSoC® 5 devices include on-chip SRAM. These families offer devices that range from 2 to 64 kilobytes.
PSoC 3 devices offer an additional 4 kilobytes as a trace buffer. Organized as up to three blocks of 4 KB each, including the 4 KB trace buffer, for CY8C38 family. Organized as up to 16 blocks of 4 KB each, for CY8C55 family. Code can be executed out of portions of SRAM, for CY8C55 family. 8-, 16-, or 32-bit accesses. In PSoC 3 devices the CPU has 8-bit direct access to SRAM. Zero wait state accesses. Arbitration of SRAM accesses by the CPU and the DMA controller. Different blocks can be accessed simultaneously by the CPU and the DMA controller. 2. 2. 5 FLASH PROGAMMING MEMORY
PSoC 3 and PSoC 5 include on-chip Flash memory. These two families offer devices that range from 16 to 256 kilobytes. Additional Flash is available for either error correction bytes or data storage. PSoC 3 and PSoC 5 Flash memory have the following features: Organized in rows, where each row contains 256 data bytes plus 32 bytes for either error correcting codes (ECC) or data storage. For PSoC 3 architecture: CY8C38 Family, organized as one block of 64, 128, or 256 rows. For PSoC 5 architecture: CY8C55 Family, organized as either one block of 128 or 256 rows, or as multiple blocks of 256 rows each. Stores CPU program and bulk or nonvolatile data For PSoC 5 architecture: CY8C55 Family, 8-, 16-, or 32-bit read accesses. PSoC 3 architecture has only 8-bit direct access.
PSoC 3 and PSoC®5 devices have on-chip EEPROM memory. These two families offer devices that range from 512 bytes to 2 kilobytes. PSoC 3 and PSoC 5 EEPROM memory have the following features: Organized in rows, where each row contains 16 bytes Organized as one block of 32, 64, or 128 rows, depending on the device Stores nonvolatile data Write and erase using SPC commands Byte read access by CPU or DMA using the PHUB Programmable with a simple command/status register interface EEPROM memory provides nonvolatile storage for user data. EEPROM write and erase operation is done using SPC commands. It may be read by both the CPU and the DMA controller, using the PHUB. All read accesses are 8-bit.
PSoC 3 and PSoC 5 architectures provide an external memory interface (EMIF) for connecting to external memory devices and peripheral devices. The connection allows read and write access to the devices.
The EMIF operates in conjunction withUDBs, I/O ports, and other PSoC 3 and PSoC 5 components to generate the necessary address, data, and control signals. The EMIF does not intercept address data between the PHUB and the I/O ports. It only generates the required control signals to latch the address and data at the ports. The EMIF generates a clock to run external synchronous and asynchronous memories. It can generate four different clock frequencies, which are the bus clock divided by 1, 2, 3, or 4. The EMIF supports four types of external memory: synchronous SRAM, asynchronous SRAM, cellular RAM/PSRAM, and NOR Flash.
External memory can be accessed via the 8051 xdata space or the ARM Cortex-M3 external RAM space; up to 24 address bits can be used. The memory can be 8 or 16 bits wide.
2. 3 System Wide Resources Clocking System
The clock system has these: Four internal clock sources increase system integration: 3 to 67 MHz Internal Main Oscillator (IMO) ±1% at 3 MHz 1 kHz, 33 kHz, 100 kHz Internal Low Speed Oscillator (ILO) outputs 12 to 67 MHz clock doubler output, sourced from IMO, MHz External Crystal Oscillator (MHzECO), and Digital System Interconnect (DSI) 24 to 67 MHz fractional Phase-Locked Loop (PLL) sourced from IMO, MHzECO, and DSI DSI signal from an external I/O pin or other logic as well as a clock source Two external clock sources provide high precision clocks: 4 to 33 MHz External Crystal Oscillator (MHzECO) 32. 768 kHz External Crystal Oscillator (kHzECO) for Real Time Clock (RTC) Dedicated 16-bit divider for bus clock Eight individually sourced 16-bit clock dividers for the digital system peripherals * Four individually sourced 16-bit clock dividers for the analog system peripherals IMO has a USB mode that auto locks to the USB bus clock, requiring no external crystal for USB. (USB equipped parts only) 2. 3. 2 POWER SUPPLY AND MONITORING PSoC 3 and PSoC 5 devices have separate external analog and digital supply pins, labeled respectively Vdda and Vddd. The devices have two internal 1. 8V regulators that provide the digital (Vccd) and analog (Vcca) supplies for the internal core logic.
The output pins of the regulators (Vccd and Vcca) have very specific capacitor requirements that are listed in the datasheet. These regulators are available: Analog regulator for the analog domain supply. Digital regulator for the digital domain supply. Sleep regulator for the sleep domain . I2C regulator for powering the I2C logic Hibernate regulator for supplying keep alive power for state retention during hibernate The Watchdog Timer (WDT) circuit automatically reboots the system in the event of an unexpected execution path. This timer must be serviced periodically.
If not, the CPU resets after a specified period of time. Once the WDT is enabled it cannot be disabled except during a reset event. This is done to prevent any errant code from disabling the WDT reset function. To use the WDT function, the user is required to enable the WDT function during their startup code. The WDT has the following features: Protection settings to prevent accidental corruption of the WDT Optionally-protected servicing (feeding) of the WDT A configurable low power mode to reduce servicing requirements during sleep mode A status bit for the watchdog event that shows the status even after a watchdog reset
2.4 Reset Power on Reset
Power on Reset (POR) is provided primarily for a system reset at power up. The IPOR will hold the device in reset until all four voltages; Vdda, Vcca, Vddd, Vccd, are to datasheet specification. The POR activates automatically at power up and consists of: An imprecise POR (IPOR) – is used to keep the device in reset during initial power up of the device until the POR can be activated A precision POR (PRES) – derived from a circuit calibrated for a very accurate location of the POR trip point. The power on RESET clears all the reset status registers
Watchdog Reset (WRES) detects errant code by causing a reset if the watchdog timer is not cleared within the userspecified time limit. The user must always set the WRES initialization code. This was done to allow the user to dynamically choose whether or not to enable the watchdog timer SOFTWARE INITIATED RESET Software Initiated Reset (SRES) is a mechanism that allows a software-driven reset. The RESET_CR2 register forces a device reset when a 1 is written into bit 0. This setting can be made by firmware or with a DMA. The RESET_SR0 [5] status bit becomes set on the occurrence f a software reset. This bit remains set until cleared by the user or until a POR reset. EXTERNAL RESET External Reset (XRES_N) is a user-supplied reset that causes immediate system reset when asserted. XRES_N is available on a dedicated pin on some devices, as well as a shared GPIO pin P1[2] on all devices. The shared pin is available through a customer-programmed NV Latch setting and supports low pin count parts that don't have a dedicated XRES_N pin. This path is typically configured during the boot phase immediately after power up.
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Seminar Report P Soc 5. (2017, Dec 13). Retrieved from https://phdessay.com/seminar-report-p-soc-5/
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