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Failure Mode of Semiconductor

3 Failure Mechanism of Semiconductor Devices Contents 3.1 Reliability Factor and Failure Mechanism of Semiconductor Devices 3- 1 3.1.

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1 Reliability factors 3- 1 3. 1. 2 Failure factors and mechanisms of semiconductor devices 3- 4 3. 2 Failure Mechanisms of Semiconductor Devices 3- 6 3. 2. 1 Time dependent dielectric breakdown (TDDB) 3- 6 3. 2. 2 Slow trap (NBTI) 3- 8 3. 2. 3 Hot carrier (AHC) 3-10 3. 2. 4 Soft error 3-12 3. 2. 5 Reliability problem of nonvolatile memory 3-14 3. 2. 6 Electromigration (EM) 3-16 3. 2. 7 Stress migration (SM) 3-20 3. 2. 8 Reliability of Cu wire 3-23 3. 2. 9 Al corrosion 3-25 3. 2. 10 Passivation crack 3-32 . 2. 11 Growth of Au/Al compound 3-35 3. 2. 12 Secondary breakdown 3-36 3. 2. 13 Thermal fatigue 3-37 3. 2. 14 Ion migration 3-38 3. 2. 15 Sn whisker 3-39 3. 2. 16 Problems in surface mounting (package cracking) 3. 2. 17 Electrostatic discharge (ESD) 3-44 3. 2. 18 i 3-40 Latch-up 3-53 Failure Mechanism of Semiconductor Devices 3. Failure Mechanism of Semiconductor Devices Reliability Factor and Failure Mechanism of Semiconductor Devices 3. 1 The reliability of semiconductor devices depends on their resistance to stresses applied to the devices, such as electric stress, thermal stress, mechanical stress, and external stress (humidity, etc. . If part of a device has a particularly weak structure, the weak part may react extremely to the applied stress, and such an extreme reaction may cause serious failures. We design semiconductor devices after thoroughly examining the internal factors that may affect their reliability, so that such internal factors can be ignored under normal use conditions. However, if a device is used under the wrong use conditions, a failure may occur. So, this section describes typical factors of failures for our customers’ reference. 3. 1. 1 Reliability factors a) Electric load (overload)

The operation conditions, such as voltage, electric current and electric power, and the combination of these operation conditions with the ambient conditions (device use conditions) greatly affect the life of semiconductor devices. The electric power may cause a rise of the junction temperature, and the rise of the junction temperature may raise the failure rate. So, the electric current should be lowered as far as possible. The voltage has the same effect as the electric power, as described above. In addition, the voltage may affect the operation of the characteristic compensation circuit.

For this reason, if the voltage is extremely low compared with the recommended operation voltage, failures may occur during operation. It is also necessary to carefully handle the surge current that flows when the switch is turned on or off and the surge voltage of inductive (L) load so that they do not exceed the maximum rated values. b) Temperature It is well known that temperature affects the life of semiconductor products. When a rapid or gradual change occurs to a device, the characteristics of the device may be deteriorated, and finally the device may malfunction.

Of course, such changes can be caused by the temperature. There is much data that proves that Arrhenius’s general formula expressing the chemical reaction rate can be used for calculation of the failure rate of semiconductors. The relation between the life “L” and the temperature “T” (absolute temperature) can be expressed as follows: Where, A: Constant Ea: Activation energy (eV) k: Boltzmann constant (8. 6 ? 10-5 eV/K) As shown above, the life will be shortened as the temperature rises. We cannot avoid this physical tendency.

When designing equipment, therefore, it is necessary that enough measures against the above tendency are taken by adopting a ventilation device, heat radiation device, or the like. T04007BE-3 2009. 4 3-1 3 Failure Mechanism of Semiconductor Devices The term “Ea” in Arrhenius’s formula is referred to as the activation energy and represents the amount of energy needed for activation of the reaction that can cause a failure. The “Ea” value depends on the failure mechanism as shown below: Defect of oxide film: 0. 3 eV to 1. 1 eV Drift of ionicity (Na ions in oxide film): 0. 7 eV to 1. 8 eV Slow trap: . 8 eV to 1. 2 eV Electromigration disconnection: for Al wire 0. 5 eV to 0. 7 eV for Cu wire 0. 8 eV to 1. 0 eV Metal (Al) corrosion: 0. 7 eV to 0. 9 eV Growth of compound between metals (Au-Al): 1. 0 eV to 1. 3 eV Figure 3. 1 shows the relationship between relative lifetime and temperature. For the graph in this figure, the lifetime at the junction temperature of 125? C (Tj = 125? C) is set to “1”. The graph shows the general tendency of the temperature dependency of the device life. Lifetime (relative value) 1000 100 eV 1. 3 rgy: V ene eV 0e ion : 1. 0. 7 ivat rgy y: Act ene erg tion en iva on

Act ati tiv Ac 10000 10 1 0. 1 0. 01 25 50 75 100 125 150 175 200 Junction temperature Tj (°C) Figure 3. 1 T04007BE-3 2009. 4 3-2 Relationship between lifetime and junction temperature Failure Mechanism of Semiconductor Devices c) Humidity The surface of each IC chip is covered with surface protective film. For this reason, IC chips are not easily affected by humidity. Resin molded devices, however, are water permeable. So, water can gradually permeate this type of device. So, if a resin molded device is operated for a long time at a high temperature and high humidity, the device may malfunction.

If it is expected that the device is operated under severe humidity conditions, it should be operated particularly carefully. d) Mechanical stress If the device is strongly vibrated during transportation, or if an extremely strong force is applied to a device during installation, the device may be directly, mechanically damaged. In addition, moisture or a contaminant may enter the device through the damaged area, and may cause deterioration of the device. e) Static electricity Equipment incorporating devices is often charged with static electricity.

You read "Failure Mode of Semiconductor" in category "Failure"
In some cases, an electrostatic charge damages the equipment.

Recently, plastic is generally used for the casing and the structure of equipment. For this reason, when our customers use our semiconductor devices for their products, we ask them to consider how to prevent electrostatic charge. In addition, human bodies can be also charged with static electricity. So, when handling semiconductor devices, it is necessary to take static charge preventive measures. You may think that electrostatic destruction is a problem peculiar to MOS devices. However, this problem also occurs on the other types of devices as the products are more miniaturized and higher frequencies are adopted.

So, any type of semiconductor device should be handled carefully. f) Effect of repeated stress When a stress is repeatedly applied, the applied stress may be stronger than steady stress. For example, a high-low temperature cycle and intermittent internal heat generation cycle can apply stresses repeatedly. The effects of these cycles, such as rearrangement of the material structure and fatigue deterioration of resistance to distortion, are examined and utilized for evaluation of failures. T04007BE-3 2009. 4 3-3 3 Failure Mechanism of Semiconductor Devices 3. 1. 2 Failure factors and mechanisms of semiconductor devices

Table 3. 1 shows the failure modes and main factors of failures. Table 3. 2 shows the ambient conditions that can accelerate failures. Table 3. 1 Failure modes and main factors of failures Crystal defect Bulk Substrate Diffusion P-N junction Device separation Crack Surface contamination Junction deterioration Impurity precipitation Mask deviation Movable ion Interface state Oxide film TDDB (time dependent dielectric breakdown) Hot carrier Corrosion Metallization Wire Via Contact Electro migration Stress migration Alloy pitting Al shift caused by resin stress Pinhole Passivation Surface protective film Layer insulation film

Crack Contamination Reversed surface Crack (stress non-uniformity, void) Die bonding Chip peeling (insufficient bonding strength) Thermal fatigue Defective substrate Peeled bond Generation of compound between metals (purple plague) Damage under bond, crack Wire bonding Bonding position deviation Wire deformation Wire breakage Short circuit between wires Cracked package Moisture absorption (lead frame, resin interface) Package Resin Lead frame Lead plating Impurity ion of resin Surface contamination Curing stress Corroded or oxidized lead Broken or bent lead Static electricity Overvoltage Use environment

Surge voltage Latch-up Software error T04007BE-3 2009. 4 3-4 Soldering error Increase in thermal resistance Resistance fluctuation Unstable operation Vt/hFE shift Impossible to withstand voltage Increase in leakage current Failure mechanism Open Failure factor Short circuit Failure mode Failure Mechanism of Semiconductor Devices Table 3. 2 Failure factors and ambient conditions for failure acceleration Symbols: = Main factor = Sub-factor Mounting Static electricity Spray of salt water Vibration Fall Shock THB/USPCBT Thermal shock Left at high temperature and high humidity Temperature cycle Left at low temperature

Left at high temperature Intermittent operation Failure mechanism High-temperature bias Low-temperature operation Failure factor High-temperature operation Ambient conditions for failure acceleration Crystal defect Bulk Substrate Diffusion P-N junction Device separation Crack Surface contamination Junction deterioration Impurity precipitation Mask deviation Movable ion Oxide film Interface state TDDB (time dependent dielectric breakdown) Hot carrier Corrosion Metallization Wire Via Contact Electro migration Stress migration Alloy pitting Al shift caused by resin stress Pinhole Passivation Surface protective film

Layer insulation film Crack Contamination Reversed surface Crack (stress non-uniformity, void) Die bonding Chip peeling Thermal fatigue Defective substrate Peeled bond Generation of compound between metals (purple plague) Wire bonding Damage under bond, crack Bonding position deviation Wire deformation Wire breakage Short circuit between wires Cracked package Moisture absorption (lead frame, resin interface) Package Resin Lead frame Lead plating Impurity ion of resin Surface contamination Curing stress Corroded or oxidized lead Broken or bent lead T04007BE-3 2009. 4 3-5 3 Failure Mechanism of Semiconductor Devices . 2 Failure Mechanisms of Semiconductor Devices 3. 2. 1 Time dependent dielectric breakdown (TDDB) As integrated circuits are miniaturized, the gate oxide films are becoming extremely thin, and in these oxide films, the electric field strength is getting ever stronger. Oxide film breakage is caused by either an initial defect or deterioration of the oxide film. The former breakage will result in an early failure, and the latter breakage will result in a long-term reliability failure. It is generally said that the true withstand voltage against dielectric breakdown is 10 MV/cm for oxide films.

For this reason, when the electric field applied to an oxide film exceeds this dielectric breakdown withstand voltage, the oxide film may be broken. However, even if an oxide film is put to practical use in an electric field of 2 MV/cm to 5 MV/cm (low enough compared with the dielectric breakdown withstand voltage of oxide films), continuous application of such a low electric field for a long time may also cause breakage as time elapses. This type of breakage is referred to as a time dependent dielectric breakdown (TDDB). Figure 3. 2 shows the dielectric breakdown withstand voltage distribution of oxide films.

Normally, there are three modes: mode A for 0 to 2 MV/cm, mode B for 2 MV/cm to 8 MV/cm, and mode C for 8 MV/cm or more. Mode A is mainly for the yield (early failure). Mode B is mainly for the main cause of failure, reliability deterioration (random failure). Mode C is for determination of the ultimate use limit (true failure) of the film. Mode A is caused by an initial defect, such as a short circuit caused by dust or a pinhole of the oxide film. Mode B is caused by a defect in oxide film forming that may be caused by oxygen precipitate on the silicon crystal surface, or other defects.

Modes A and B can be improved by optimizing the process. Regarding the TDDB (time dependent dielectric breakdown), the TDDB life in practical use should be determined, because dielectric breakdown occurs as the time elapses even if the electric field is much lower than the dielectric breakdown withstand voltage of the oxide film. So, we carry out the accelerated test to assume the practical use life. The following empirical formula expresses the TDDB life: Where, t: Life in practical use (h) tt: Life in test (h) ?: Electric field acceleration factor E: Electric field strength in practical use (MV/cm)

Et: Electric field strength in test (MV/cm) Ea: Activation energy (eV) k: Boltzmann constant (eV/K) T: Temperature for actual use (K) Tt: Test temperature (K) Normally, for oxide films, the “? ” value is in the range of -1 to -2, and the “Ea” value is in the range of 0. 3 eV to 1. 1 eV. Figure 3. 3 through Figure 3. 6 show the electric field/temperature accelerated test results as examples. T04007BE-3 2009. 4 3-6 Failure Mechanism of Semiconductor Devices By the way, it is well known that failure distribution can be Weibull distribution or logarithmic normal distribution.

In addition, the failure distribution greatly depends on the process. If the dielectric breakdown withstand voltage values are greatly dispersed for a process, the failures will be distributed in a wide range, and in some cases, early failures or random failures may occur. There are several effective methods to prevent these failures. They are: to optimize the process and to form an oxide film having less defects, to properly control the process (to control the dielectric breakdown withstand voltage of gate oxide film, etc. ), and to carry out screening by applying high electric field during inspection or burn-in.

Various models can be considered for TDDB. Basically, TDDB is closely related to traps that are formed in oxide films when a high electric field stress is applied. When a high electric field stress is applied, electrons will be output from the cathode and become implanted in the oxide film. These electrons will become hot electrons, and collide with the crystal lattice to generate more electrons and positive holes. When these electrons are caught in a trap, a local high electric field will be formed, and Si-O binding of the oxide film will be broken, and finally dielectric breakdown will occur.

In addition, as the processes are miniaturized, the gate oxide films are becoming thinner, and their film thickness is now several nm. As a result, we now have a new problem: deterioration of oxide films caused by plasma damage in the process. Effective measures for this problem are to adopt a process that ensures less damage and to adopt a structure that cannot be easily damaged by plasma, while referring to the circuit design rules. Degree 30 20 10 2 4 6 8 10 12 Applied voltage (V) Figure 3. 2 Dielectric breakdown withstand voltage distribution for oxide films 2 Stress temperature Ta = 125°C 1 50% -2 10MV/cm TDDB life lnln(1/(1-F)) -1 9. 0MV/cm -3 9. 5MV/cm -4 -5 -6 0. 1% -7 Stress time Figure 3. 3 Result of electric field accelerated test 5 6 7 8 9 10 11 Electric field of stress [MV/cm] Figure 3. 4 Dependency on electric field shown in accelerated test T04007BE-3 2009. 4 3-7 3 Failure Mechanism of Semiconductor Devices 2 Electric field of stress E = 9. 5 MV/cm 1 50% TDDB life lnln(1/(1-F)) 0 -1 -2 150°C 100°C 125°C -3 -4 -5 -6 200°C 0. 1% -7 2 Stress time Figure 3. 5 100°C 2. 5 2. 75 3 1000/Absolute temperature [K-1] Result of temperature Figure 3. 6 accelerated test 3. 2. 2 150°C 2. 25 Dependency on temperature shown in accelerated test Slow trap (NBTI)

The MOS transistor and the MOSIC are devices that essentially utilize the surface phenomenon of semiconductors. The characteristics of these devices are greatly affected by various types of electric charge existing in the gate oxide films. In some cases, electric charge may cause malfunction of the devices. It is well known that the following four types of electric charge can exist in gate oxide films3. 1,2,3): (1)Mobile ionic charge Qm (2)Fixed oxide charge Qf (3)Interface trapped charge Qit (4)Oxide trapped charge Qot Figure 3. 7 shows the positions of these types of electric charge in the oxide film. METAL Na+ MOBILE IONIC + CHARGE(Qm)

K OXIDE TRAPPED CHARGE(Qot) SiO2 + – + – + + + FIXED OXIDE CHARGE(Qf) + + + + SiOx INTERFACE TRAPPED CHARGE(Qit) Si Figure 3. 7 Various types of electric charge in oxide film At the early stages of MOS transistor development, application of positive voltage to the gate electrode may greatly change the threshold voltage (Vt) value in the negative direction (see Figure 3. 8). On the other hand, application of negative voltage may slightly change the Vt value in the positive direction. This is because application of voltage will move the Na+ ions in the gate oxide film to the interface between SiO2 and Si to cause T04007BE-3 2009. 3-8 Failure Mechanism of Semiconductor Devices an electric charge on the Si surface. This unstable phenomenon, however, has been improved by adopting clean SiO2, forming a clean gate electrode, utilizing the Na+ ion gettering effect of phosphorus (P), etc. Cmeas Front B-T Gate electrode Gate oxide film Drain Na+ Na e- + Na+ ee- Na+ e- Na+ e- Source Rear B-T VG Si substrate Figure 3. 8 Determination of movable ionic charge by CV measurement However, application of voltage at a high temperature to the above-described clean oxide film may also cause change in the Vt.

Different from the Na+ ion case as described above, application of negative voltage to the gate electrode will change the Vt in the negative direction. In this way, if the Vt changes in the same direction as the voltage applied to the gate electrode, such a phenomenon is generally referred to as the implanting type shift. When the MOS transistor is tested at a high temperature by applying voltage, the Vt shift may occur. As shown in Figure 3. 9, the Vt shift greatly depends on the strength of the electric field applied to the gate electrode. This phenomenon is particularly noticeable when a negative voltage is applied.

As semiconductor integrated circuits are more and more miniaturized, the gate oxide films are becoming thinner and thinner. So the electric field strength applied to gate electrodes are becoming stronger and stronger. Regarding the CMOS devices, since negative voltage is applied to the gate of the P-channel transistor, this type of Vt shift may occur on the CMOS devices, and such a problem should be solved. For this type of Vt shift, there are the following mechanisms: 1) The thermally excited positive holes exceed the potential barrier of the interface.

Carriers, therefore, are trapped near the interface. 2) When a high electric field is applied, the Si-H binding existing at the interface between Si and SiO2 will be broken, and the interface state will be generated. In addition, a positive electric charge will be caused near the interface. Regarding the injection type shift, if the Vt shifts depending on the carrier movement at the interface between Si and SiO2, such a Vt shift is referred to as the slow trapping phenomenon or negative bias temperature instability (NBTI).

By the way, it is confirmed that this type of Vt shift depends on the package or the protective film, and is affected by external impurities (see Figure 3. 10). For this reason, if plasma SiN is adopted for the protective film, this type of Vt shift can be prevented. T04007BE-3 2009. 4 3-9 3 Failure Mechanism of Semiconductor Devices 10 P-channel transistor 150°C II circuit 0 P-channel transistor II circuit 102 V ?20 Va: V ?15 V ?10 V V ?9 ?13 102 a b c 103 104 (h) V ?15 10V ? ?6V 10 Ta=175°C Ta=150°C 1 1 102 10 103 104 Testing time (h) : SiO2, plastic b: SiO2, ceramic c: SiN, plastic Figure 3. 9 Dependency on applied voltage and temperature 3. 2. 3 Figure 3. 10 Influence of protective film and package Hot carrier (AHC) One of the most significant problems in ensuring the reliability of micro MOS devices is deterioration of the transistor characteristic caused by hot carrier injection3. 4,5). This is because it is difficult to reduce the power supply voltage for devices that are being ever more miniaturized, so the electric field strength in the transistor is continually increasing. Hot carrier” is a generic name for high-energy hot electrons and high-energy hot holes (positive holes) generated in the transistor. Table 3. 3 shows the hot carrier generation mechanism. As shown in Table 3. 3, there are channel hot electrons (CHE), avalanche hot carriers (AHC), and substrate hot electrons (SHE). Among them, AHC shows remarkable change when devices are miniaturized. T04007BE-3 2009. 4 3-10 Failure Mechanism of Semiconductor Devices Table 3. 3 Hot carrier generation and bias conditions Type VGS = VDS, VSX < 0 Bias condition Source

Gate VGS VGS = 1/2VDS, VSX < 0 Drain VDS VGS VGS > 0, VDS = GND, VSX < 0 VGS VDS Hot carrier implanting model VSX Substrate (a) VSX (c) ? BN B A B Example of a circuit that can easily generate hot IN carriers VSX (c) A OUT VSX (b) Transfer gate (d) Bootstrap circuit9) (f) Capacity construction for Figure (d) Note: VGS = Voltage between gate and source, VDS = Voltage between drain and source, VSX = Voltage between substrate and source, = Electron, = Hole AHC is easily generated when the gate voltage is slightly lower than 1/2 of the drain voltage.

At this point, the carriers flowing through the channel will impact the Si crystal lattice to generate pairs of a hot electron and a hot hole. These pairs function as hot carriers. When hot carriers are injected into a gate oxide film, the gate oxide film may be charged, or the Si-SiO2 interface may be damaged. As a result, the transistor characteristic may be changed. The amount of hot carriers implanted into the gate oxide film cannot be directly measured, but can be indirectly assumed from the substrate current (current of hot holes generated by impact ionization). Figure 3. 1 shows the relationship between the VT change rate, the substrate current, and the voltage between gate and source when the VDS is constant. As shown in Figure 3. 11, when the VDS value is almost twice as much as the VGS value (2VGS = VDS), the substrate current will be maximized. At this point, the AHC shows a remarkable characteristic change. To carry out a test, the gate voltage is generally set to the point where the substrate current can be maximized. Hot carriers injection into a gate oxide film may generate the interface state and fixed charge, and may finally deteriorate the Vt and the gm of the FET.

Figure 3. 12 shows deterioration of the Id-Vg characteristic of the transistor as an example. As shown in the figure, as the Vt of the FET is increased, the circuit operation will become slow, and will finally operate abnormally (see Figure 3. 13). To improve the resistance to hot carriers, a special transistor structure (LDD) is adopted for recent microdevice processes because this special transistor structure can lower the electric field near the drain. T04007BE-3 2009. 4 3-11 3 Failure Mechanism of Semiconductor Devices 16 Voltage between drain and source: 12 V 3 12 2 8 1 4 0

Substrate current ISUB (arbitrary unit) VT change rate at certain time (arbitrary unit) 4 Drain current Id (? A) 200 100 0 0 2 4 6 8 10 12 0 0 1 Voltage between gate and source VGS (V) Figure 3. 11 Relationship between VT change rate, 2 Gate voltage Vg (V) Figure 3. 12 substrate current and voltage between gate and source Deterioration of Id-Vg characteristic (Example) side-wall As P DDD structure Figure 3. 13 3. 2. 4 As LDD structure Hot carrier resistant structure (Example) Soft error As the devices are miniaturized, we have a new problem, that is, abnormal operation of devices that is caused by ? articles radiated from a very small amount of radioactive elements (uranium (U), thorium (Th), etc. ) that are contained in the package material. This problem is referred to as a soft error. This abnormal operation, however, is temporary. So writing data again can restart normal operation. This problem is caused by miniaturization of devices. As the devices are miniaturized, the electric charge of signals handled in the devices is lowered. As a result, the electric charge of the noise generated by ? particles that are radiated in the chip has a large impact that cannot be ignored.

Figure 3. 14 shows that ? particles are generated at the cell capacitor that stores 1-bit data (1 bit = minimum data unit of dynamic RAM). The generated ? particles generate electron-hole pairs in the substrate. While generating the electron-hole pairs, the ? particles will reduce their energies. The electrons generated in this process can invert the data of the cell capacitor. This means that a cell capacitor judges whether electrons exist (data “L”) or do not exist (data “H”). So if electrons are generated in the cell capacitor by ? particles, data “H” will be inverted to data “L”.

This is referred to as a soft error in the memory cell mode. T04007BE-3 2009. 4 3-12 Failure Mechanism of Semiconductor Devices The cell capacitor data is read out to the bit line by diffusion, and then compared with the reference potential. If electrons generated by ? particles flow into the bit line, the potential of the read out data or the reference potential may be lowered. If the data potential is lowered, data will be inverted from “H” to “L”. If the reference potential is lowered, the data will be inverted from “L” to “H”. This is referred to as a soft error in the bit line mode.

If the operation cycle (cycle time) of the dynamic RAM is shortened, the reference potential will be compared with the data potential more frequently. As a result, soft errors in the bit line mode will be increased. On the other hand, change in the cycle time will not affect the soft errors in the memory cell mode. When data is “H” When data is “H” WORD LINE WORD LINE BIT LINE BIT LINE n+ ? ray n+ p p The ? ray shot from the package will enter the Si substrate, and will generate electronhole pairs. The electrons separated in the depletion layer of the substrate will be ccumulated up to the memory cell capacity, and finally the data will be inverted. Figure 3. 14 Soft error in memory cell mode Figure 3. 15 shows dependency of the soft error rate on the cycle time. In some cases, the soft error rate depends on the cycle time, but in the other cases, the soft error rate does not depend on the cycle time. If the cycle time is long, it seems that soft errors in the memory cell mode occur more frequently. If the cycle time is short, it seems that soft errors in the bit line mode occur more frequently. T04007BE-3 2009. 4 3-13 3

Failure Mechanism of Semiconductor Devices Soft error rate (relative value) 103 Soft errors in experiment 102 Memory cell mode (“H”>”L”) Bit line mode (“L”>”H”) 101 1 10 Operation speed (? s) Figure 3. 15 Dependency of soft error rate on cycle time There are several measures to prevent soft errors caused by ? particles. These measures are material that contains less radioactive elements (? particle generative source), entering the chip by coating organic material on the chip, and to use a package to prevent ? particles from to properly design devices (improvement of he bit line structure using wire materials of Al, poly-Si, etc. , improvement of the sense amplifier, adoption of the return bit line, etc. ). In this way, we adopt various measures to increase reliability. 3. 2. 5 Reliability problem of nonvolatile memory EPROMs and EEPROMs were conventionally used as nonvolatile memories. In recent years, however, flash memories have been preferred. So, this section describes the reliability of a typical flash memory as an example. Compared with EEPROMs (conventional nonvolatile memories), flash memories can erase a lot of bit data at a time.

This means that flash memories have enabled mass storage in nonvolatile memories. In 1984, the principle of flash memory was proposed3. 6). Since then, flash memories have been rapidly developed and sold as new products. During this period, since there are various demands, such as higher integration, more rewritable memory, and higher speed, flash memory cells having various structures have been developed to reduce the size, to enable mass storage, and to ensure higher speed3. 7,8). When the flash memory is roughly classified from the viewpoint of use, there are two types of flash memory.

One type is the high-speed random access type that is embedded in microcomputers in place of mask ROMs. The other type is the serial access type that enables mass storage and allows rewriting many times. This section describes the stack gate type flash memory which is typical structure for embedded in microcomputers. To write or erase data, the methods shown in Figure 3. 16 are used. T04007BE-3 2009. 4 3-14 Failure Mechanism of Semiconductor Devices Vcg (Vcg>Vd) Vd Control gate (CG) Floating gate (FG) Vd n+ n+ source Tunnel oxide film drain (open) Vpp n+ n+ drain source Erase Write Id(1) ‘1’ ‘0’ 0’ Id [ uA ] Id [ uA ] ‘1’ Id(0) read 0 0 Vcg [ V ] (a) Writing operation Figure 3. 16 read Vcg [ V ] (b) Erasing operation Stack gate type flash memory cell (CHE: Write / FN: Erase) a) Retention (charge retention) As shown in Figure 3. 17(a), if retention (charge retention) occurs, a very small amount of electric charge will be gradually discharged from the floating gate that is isolated from the outside, and finally the data will be rewritten. Retention also occurred on conventional nonvolatile memories, such as EPROMs and EEPROMs. So retention was a problem common to all the nonvolatile memories.

To prevent this problem, we have been optimizing the quality of the tunnel oxide film, etc. b) Read-out gate disturb3. 9) As shown in Figure 3. 17(b), if a read-out gate disturb occurs, application of voltage to the control gate will allow electrons to enter the floating gate from the substrate, and finally the data will be rewritten. This is a reliability problem peculiar to flash memories. Just below the floating gate, any flash memory has an oxide film, and different from the other memory devices, this oxide film entirely consists of a thin tunnel oxide film.

For this reason, this problem, read-out gate disturb, occurred on flash memories more frequently. To ensure reliability, we have adopted some measures, such as optimization of the drain-source structure, optimization of tunnel oxide film forming process, and adoption of a data rewriting method that can reduce damage of the tunnel oxide film. T04007BE-3 2009. 4 3-15 3 Failure Mechanism of Semiconductor Devices control gate Vcg 5 . 5 V Control gate Floating gate n+ drain 1 . 1 V n+ n+ source n+ source Vd drain BL 1. 1 V Data: ‘0’ > ‘1’ 0V WL 5. 5 V

Data: ‘1’ > ‘0’ (a) Retention Figure 3. 17 3. 2. 6 (b) Read-out gate disturb Flash memory retention and read-out gate disturb Electromigration (EM) Electric current flowing to a conductor may move metal ions. This phenomenon is referred to as electromigration3. 10,11,12). If Al wire is used, Al ions will move in the same direction as the electron flows, and finally voids may be generated on the cathode side and the problem of open circuit failures may be caused. On the anode side, hillocks and whiskers may grow, and in the worst case, shortcircuit may occur.

Electromigration is one of diffusion phenomena that can be caused by interaction between metal atoms in a conductor and electrons that pass through the conductor. Metal atoms in a conductor are heat-vibrated in the energy potential well. If the energy of an atom is increased and exceeds a certain point, the atom will be released from the energy potential well to move freely (to become a free atom). Such self-diffusion, however, just causes rearrangement among metal atoms, and no change can be seen from the macro point of view. As shown in Figure 3. 18, interaction between free atoms and current (electrons) can finally move the atoms.

When the current density is in the range of 105 A/cm2 to 106 A/cm2, Al atoms will be diffused into the crystal lattice or the grain boundary by exchanging the momentum with free electrons. Figure 3. 19 shows an example of electromigration phenomenon. When generation of voids is started, the cross-section area of the conductor will be reduced, but the current density will be further increased. In addition, the temperature will rise due to the Joule heat, etc. , and growth of the voids will be further accelerated. Finally, disconnection will occur. T04007BE-3 2009. 4 3-16 Failure Mechanism of Semiconductor Devices

Electric field (-) – F2 (+) Al+ F1 F1 Figure 3. 18 F2/10 Force acting between Figure 3. 19 metal atoms Example of electromigration phenomenon The following formula is generally used for expression of the mean time to failure due to electromigration: MTTF = A J-nexp(Ea/kT) Where, MTTF : Mean time to failure (h) A : Constant of wire J : Current density (A/cm2) n : Constant Ea : Activation energy (eV) k : Boltzmann constant (eV/K) T : Absolute temperature of wire (K) It is reported that the “n” value is in the range of 1 to 3, and the “Ea” value is in the range of 0. 5 eV to 0. 7 eV.

The following factors can reduce the failures caused by electromigration: a) Crystal structure (grain diameter, crystal orientation, etc. ) b) Addition of other elements to metal film c) Laminated wiring structure a) Crystal structure Electromigration is caused by grain boundary diffusion or surface diffusion. For this reason, the mean time to failure depends on the structure of the thin film, and particularly depends on the crystal grain diameter and uniformity. As shown in Figure 3. 20, there are several types of diffusion for metal atoms: lattice diffusion, grain boundary diffusion, and surface diffusion.

Polycrystal films frequently cause grain boundary diffusion. In addition, since the metal atoms caught in the grain boundary do not have large activation energy, electromigration is mostly caused by grain boundary diffusion. Moreover, since the surface area is large compared with the volume, surface diffusion cannot be ignored. For this reason, if the grain diameter is increased for a wire film, the grain boundary density will be reduced, and as a result, the mean time to failure can be prolonged. T04007BE-3 2009. 4 3-17 3 Failure Mechanism of Semiconductor Devices

If the grain diameter is increased for a wire film, the crystal direction will be arranged in the direction. For this reason, discontinuity in the wire can be reduced, and electromigration can be restricted. Figure 3. 213. 13) shows the relationship between the grain diameter and the mean time to failure in the case of electromigration. As shown in the figure, the mean time to failure of the film with large grain diameter (8 ? m) is 9 times longer than that of small grain diameter (approx. 1. 2 ? m). Average grain diameter s (? m) 0. 1 1 10 10 106 100 1000 Dgb Dl Mean time to failure (h) Ds 105 104 I s ? · log I (Al-0. %Cu,80°C,1 ? 105A/cm2) Ds: Surface diffusion Dl: Lattice diffusion Dgb: Grain boundary diffusion Figure 3. 20 Diffusion in Al thin film ( Figure 3. 21 ) Relationship between mean time to failure and grain diameter (s), grain diameter dispersion (? ), or crystal direction b) Addition of other elements to metal film Addition of other elements to the Al thin film will have the greatest effect on improvement of the mean time to failure in case of electromigration. There are some elements that are effective in improving the mean time to failure in case of electromigration. These elements are Cu, Ti, Ni, Co, Cr and (Si).

Addition of Si, however, will be effective only if the temperature is high, but will not be effective if the temperature is 120°C or less. So, Si is added to prevent diffusion of Al at the Al-Si contact area. Addition of other elements is effective in restricting electromigration because grain boundary diffusion can be restricted by the added elements. Specifically, addition of other elements will reduce the number of holes existing in the grain boundary. As a result, diffusion in the grain boundary will be reduced, and electromigration will be restricted and the mean time to failure will be prolonged.

Figure 3. 223. 14) shows an example of a case in which the mean time to failure could be prolonged (electromigration could be restricted) by adding an element “Cu”. T04007BE-3 2009. 4 3-18 Cumulative failure rate (%) Failure Mechanism of Semiconductor Devices 99. 9 ECL100K 150°C 60mA 90 50 Al-Si Al-Si-Cu 10 5 2 102 103 104 Testing time (h) Figure 3. 22 Effect of added element “Cu” c) Laminated wiring structure Adoption of the laminated structure is effective in prolonging the mean time to failure in case of electromigration.

For this laminated structure, barrier metals having a high melting point, such as Ti, TiN and TiW, should be adopted. The laminated structure can improve crystallization of the Al wire on the barrier metal, and the barrier metal is not easily disconnected compared with the Al wire. For this reason, the laminated structure can prolong the mean time to failure. Figure 3. 233. 15) shows an example of a case where the mean time to failure could be prolonged (electromigration could be restricted) in case of electromigration Cumulative failure probability (%) by adopting the laminated wiring structure. 99. 9 6 2

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